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high accuracy ultralow i q , 300 ma, anycap low dropout regulator adp3333 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights o f analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.31 13 ? 2001 C 2009 analog devices, inc. all rights reserved. features high a ccuracy over l ine and l oad: 0.8% @ 25 c, 1.8% o ver t emperature ultralow d ropout v oltage: 230 mv ( m ax imum ) @ 300 ma requires o nly c out = 1.0 f for s tability anycap is s table with a ny t ype of c apacitor (i ncluding mlcc) current and t hermal l imiting low n oise low s hutdown c urrent: < 1 a 2.6 v to 12 v s upply r ange ? 40 c to +85 c a mbient t emperature r ange ultrasmall 8 -l ead msop p ackage applications cellular p hones pcmcia c ards personal d igital a ssistants (pdas) dsp/asic s upplies functional block dia gram thermal protection cc in adp3333 out gnd q1 band gap ref driver g m sd r1 r2 02615-001 figure 1. general description the adp3333 is a member of the adp333x family of precision low dropout (ldo) any cap ? voltage regulators. pin compatible with the max8860, the adp3333 operates with a wider input voltage range of 2.6 v to 12 v and delivers a load current up to 300 ma. adp3333 s tands out from other conventional ldos with a novel architecture and an enhanced process that enables it to offer performance advantages over its competition. its patented design requires only a 1.0 f output capacitor for stability. this device is insensitive to output capacitor equivalent series resistance (esr) and is stable with any good quality capacitor, including ceramic (mlcc) types for space - restricted applications. the adp3333 achieves excep tional accuracy of 0.8% at room temperature and 1.8% over temperature, line, and load variations. the dropout voltage of the adp3333 is only 140 mv (typical) at 300 ma. this device also includes a safety current limit, thermal overload protection, and a shutdown feature. in shutdown mode, the ground current is reduced to less than 1 a. the adp3333 has ultralow quiescent current, 70 a (typ ical ) in light load situations. adp3333 nc in gnd v out on off out sd nc = no connect 4 1 2 7 3 + c out 1f c in 1f v in + 02615-002 figure 2. typical application circuit
adp3333 rev. b | page 2 of 1 2 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descript ions ............................. 5 typical performance characteristics ............................................. 6 theory of operation .........................................................................9 applications information .............................................................. 10 capacitor selection .................................................................... 10 output current limit ................................................................ 10 thermal overload protection .................................................. 10 calculating junction temperature ........................................... 10 shutdown mode ......................................................................... 10 pcb layout considerations ...................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 4 /09 rev. a to rev. b changes to voltage accuracy , line regulation, load regulation, and dropout voltage parameters, table 1 ................ 3 changes to table 2 ............................................................................ 4 added thermal resistance section and table 3; renumbered sequentially ....................................................................................... 4 changes t o table 4 ............................................................................ 5 changes to figure 5 and figure 7 ................................................... 6 changes to figure 10, figure 11, figure 13, and figure 15 ......... 7 changes to figure 16 and figure 17 ............................................... 8 changes to output capacitor section and calculating junction temperature section ...................................................................... 10 updated outline dimensions ....................................................... 11 changes to ordering guide .......................................................... 11 8/03 data sheet c hanged from rev. 0 to rev. a changes to figure 1 ........................................................................... 1 updated output capacitor s ection .............................................. 10 updated calculating j unction temperature s ection ................. 10 updated o utline d imensions ....................................................... 11 updated ordering guide .............................................................. 11
adp3333 rev. b | page 3 of 12 specifications v in = 6.0 v, c in = c out = 1.0 f, t j = ? 40 c to +125 c, unless otherwise noted. table 1 . parameter 1 symbol condition min typ max unit output voltage accuracy 2 v out v in = v outnom + 0.3 v to 12 v , i l = 0.1 ma to 3 00 ma , t j = 25c ? 0.8 + 0.8 % v in = v outnom + 0.3 v to 12 v , i l = 0.1 ma to 300 ma ? 1.8 +1.8 % line regulation 2 v in / v out v in = v outnom + 0.3 v to 12 v , t j = 25c 0.04 mv/v load regulation v out / i out i l = 0.1 ma to 300 ma , t j = 25c 0.04 mv/ma dropout voltage v drop out v out = 98% of v outnom i l = 300 ma 140 230 mv i l = 200 ma 105 185 mv i l = 0.1 ma 30 mv peak load current i ldpk v in = v outnom + 1 v 600 ma output noise v noise f = 10 hz to 100 khz, c l = 10 f , i l = 300 ma 45 v rms ground current in regulation i gnd i l = 300 ma 2.0 5.5 ma i l = 300 ma, t j = 25c 2.0 4.3 ma i l = 300 ma, t j = 85c 1.5 3.3 ma i l = 200 ma 1 .4 ma i l = 10 ma 200 275 a i l = 0.1 ma 70 100 a in dropout i gnd v in = v outnom ? 100 mv , i l = 0.1 ma 70 190 a v in = v outnom ? 100 mv , i l = 0.1 ma, t j = 0c to 125c 70 160 a in shutdown i gndsd sd = 0 v , v in = 12 v 0.01 1 a shutdown threshold voltage v thsd regulator on 2.0 v regulator off 0.4 v sd i input current sd 0 sd 12 v 0.85 7 a 0 sd 5 v 0.8 4.5 a output current in shutdown i osd t j = 25c, v in = 12 v 0.01 1 a t j = 125c, v in = 12 v 0.01 1 a 1 application stable with no load. 2 v in = 2.6 v for models with v outnom 2.3 v.
adp3333 rev. b | page 4 of 12 absolute maximum rat ings table 2. parameter rating input supply voltage ? 0.3 v to +16 v shutdown input voltage ? 0.3 v to +16 v power dissipation internally limited operating ambient temperature range ? 40c to +85c operating junction temperature range ? 40c to +125c soldering conditions jedec j - std -020 stresses above those l isted under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not i mplied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja unit 8- lead msop (4 - layer) 158 c/w 8- lead msop (2- layer) 220 c/w esd caution
adp3333 rev. b | page 5 of 12 pin configuration and function descripti ons 1 2 3 out in gnd nc 1 4 nc 8 sd 7 nc 6 nc 5 nc = no connect adp3333 top view (not to scale) 1 can be connected to any other pin. 02615-003 figure 3. pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 out output of the regulator. bypass to ground with a 1.0 f or larger capacitor. 2 in input pin. bypass to ground with a 1.0 f or larger capacitor. 3 gnd ground pin. 4 to 6, 8 nc no connect. best thermal performance is achieved when the nc pins are connected to the gnd plane . 7 sd active low shutdown pin. connect to ground to disable the regulator output. when shutdown is not used, connect this pin to the in pin.
adp3333 rev. b | page 6 of 12 typical performance characteristics output voltage (v) 2.502 2.500 2.498 2.496 2.494 2.492 2.490 2.488 input voltage (v) 3 4 5 6 7 8 9 10 11 12 0ma 100ma 200ma 300ma v out = 2.5v 02615-004 figure 4. line regulation outp ut voltage vs. input voltage output current (ma) output voltage (v) 2.502 2.500 2.494 2.492 2.490 2.488 2.498 2.496 0 50 100 150 200 250 300 v in = 6v v out = 2.5v 02615-005 figure 5. output voltage vs. output current input voltage (v) 140 60 0 120 100 40 20 80 ground current (a) i l = 100a i l = 0a v out = 2.5v 0 2 4 6 8 10 12 02615-006 figure 6. ground current vs. input voltage output current (ma) ground current (ma) 0 0.5 1.0 1.5 2. 0 2. 5 0 50 100 150 200 250 300 v in = 6v 02615-007 figure 7. ground current vs. output current output change (%) 1.0 0.5 0.6 0.9 0.8 0.7 0 0.2 0.1 0.4 0.3 ?0.2 ?0.3 ?0.1 ?0.4 0ma 200ma 300ma junction temperature (c) ?50 ?25 0 25 50 75 100 125 0ma 02615-008 figur e 8. output voltage variation % vs. junction temperature ground current (ma) 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 junction temperature (c) v in = 6v i l = 100ma i l = 200ma i l = 300ma i l = 0ma ?50 ?25 0 25 50 75 100 125 02615-009 figure 9. ground current vs. junction temperature
adp3333 rev. b | page 7 of 12 output current (ma) input/output voltage (mv) 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 300 250 200 150 100 50 0 02615-010 figure 10 . dropout voltage vs. output current time (seconds) 3.0 2.5 2.0 1.5 1.0 0.5 0 input/output voltage (v) 1 2 3 4 02615-011 v out = 2.5v sd = v in r l = 8.3 ? v in v out figure 11 . v out during power - up/power - down 3 2 1 0 4 2 0 v out (v) v in (v) 200 400 600 800 time (s) c out = 1f c out = 10f v out = 2.5v sd = v in r l = 8.3 ? 02615-012 figure 12 . power - up response 3.00 3.50 2.49 2.50 2.51 2.52 time (s) 40 80 140 180 v out (v) v in (v) v out = 2.5v r l = 8.3 ? c l = 1f 02615-013 figure 13 . line transient response , c l = 1 f 3.00 3.50 2.49 2.50 2.51 2.52 time (s) 40 80 140 180 v out (v) v in (v) v out = 2.5v r l = 8.3 ? c l = 10f 02615-014 figure 14 . line transient response , c l = 1 0 f 10 2.4 2.5 2.6 i out (ma) 300 2.7 v out (v) time (s) 200 400 600 800 v in = 4v v out = 2.5v c l = 1f 02615-015 figure 15 . load transient response , c l = 1 f
adp3333 rev. b | page 8 of 12 10 2.4 2.5 2.6 i out (ma) 300 2.7 v out (v) time (s) 200 400 600 800 v in = 4v v out = 2.5v c l = 10f 02615-016 figure 16 . load transient response , c l = 10 f 0 1 2 3 0 2.5 i out (a) v out (v) time (s) 200 400 600 800 v in = 6v v in = 3.6v 02615-017 figure 17 . short - circuit current 0 0 2 1 2 3 v out v sd sd 1f 1f 10f 10f time (s) 200 400 600 800 v in = 6v v out = 2.5v r l = 8.3 ? 02615-018 figure 18 . turn - on /turn - off response frequency (hz) ripple rejection (db) ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 10 100 1k 10k 100k 1m 10m c l = 10f i l = 500ma c l = 10f i l = 50a v out = 2.2v c l = 1f i l = 500ma c l = 1f i l = 50a 02615-019 figure 19 . power supply ripple rejection 0ma 0 20 40 60 80 120 100 300ma 0 10 20 30 40 50 c l (f) rms noise (v) 02615-020 figure 20 . rms noise vs. c l (10 hz to 100 khz) frequency (hz) 100 10 1 0.1 0.01 0.001 10 100 1k 10k 100k 1m v out = 2.5v i l = 1ma c l = 1f c l = 10f voltage noise spectral density (v/ hz) 02615-021 figure 21 . output noise density
adp3333 rev. b | page 9 of 12 theory of operati on the adp3333 anycap ldo uses a single control loop for regulation and reference functions (see figure 22 ). the output voltage is sensed by a resistive voltage divider consisting of r1 and r2 that is varied to provide the availa ble output voltage option. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. input q1 adp3333 compensation capacitor r1 d1 r2 r3 r4 output ptat current (a) fb gnd g m r l c l ptat v os attenuation (v band gap /v out ) noninverting wideband driver 02615-022 figure 22 . functional block diagram a very high gain error ampli fier is used to control this loop. the amplifier is constructed in such a way that at equilibrium it produces a large, temperature - proportional input offset voltage that is repeatable and very well controlled. the temperature proportional offset voltage i s combined with the complementary diode voltage to form a virtual band gap voltage, implicit in the network, although it never appears explicitly in the circuit. ultimately, this patented design makes it possible to control the loop with only one amplifier . this technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade - off of noise sources and leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the band gap voltage to the output voltage. although the r1/r2 resistor divider is loaded by the diode , d1 , and a second divider consisting of r3 and r4, the values can be chosen to produce a temperature stable output. this unique arrangement specifically corrects for the loading of the div ider so that the error resulting from base current loading in conventional circuits is avoided. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this special noninverting driver enables th e frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type, and esr of the load capacitance. most ldos place very strict requirements on the range of esr values for the output ca pacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance . moreover, the esr value required to keep conventional ldos stable changes depending on load and temperature. these esr limitations make designing wit h ldos more difficult because of their unclear specifications and extreme variations over temperature. with the adp3333 anycap ldo, this is no longer true. this device can be used with virtually any good quality capacitor, with no constraint on the minimu m esr. its innovative design allows the circuit to be stable with just a small 1 .0 f capacitor on the output. additional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain, which leads to excellent l ine and load regulation. an impressive 1.8% accuracy is guaranteed over line, load, and temperature. additional features of the circuit include current limit and thermal shutdown.
adp3333 rev. b | page 10 of 12 applications information capacitor selection output capacitor the stability and transient response of the ldo is a function of the output capacitor. the adp3333 is stable with a wide range of capacitor values, types, and esr (anycap). a capacitor as low as 1.0 f is all that is needed for stability. larger capacitors can be used if high current surges on the output are anticipated. the adp3333 is stable with extremely low esr capacitors (esr 0), such as multilayer ceramic capacitors (mlcc) or oscon. note that the effective capacitance of some capacitor types falls below the minimum rated value over temperature or with dc voltage. ensure that the capacitor provides at least 1.0 f of capacitance over temperature and dc bias. input bypass capacitor an input bypass capacitor is not strictly required but is recom- mended in any application involving long input wires or high source impedance. connecting a 1.0 f capacitor from the input to ground reduces the circuits sensitivity to printed circuit board (pcb) layout and input transients. if a larger output capacitor is necessary, then a larger value input capacitor is also recommended. output current limit the adp3333 is short-circuit protected by limiting the pass transistors base drive current. the maximum output current is limited to about 1 a (see figure 17). thermal overload protection the adp3333 is protected against damage due to excessive power dissipation by its thermal overload protection circuit. thermal protection limits the die temperature to a maximum of 165c. under extreme conditions (that is, high ambient temperature and power dissipation) where the die temperature starts to rise above 165c, the output current is reduced until the die temperature drops to a safe level. current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, the devices power dissipation should be externally limited so that the junction temperature does not exceed 125c. calculating junction temperature device power dissipation is calculated as follows: p d = ( v in ? v out ) i l + ( v in ) i gnd where i l and i gnd are the load current and ground current, and v in and v out are the input and output voltages, respectively. assuming the worst-case operating conditions are i l = 300 ma, i gnd = 2.0 ma, v in = 4.0 v, and v out = 3.0 v, the device power dissipation is p d = (4.0 v ? 3.0 v) 300 ma + (4.0 v) 2.0 ma = 308 mw the package used on the adp3333 has a thermal resistance of 158c/w for 4-layer boards. the junction temperature rise above ambient is approximately equal to t ja = 0.308 w 158c/w = 48.7c therefore, to limit the junction temperature to 125c, the maximum allowable ambient temperature is t a(max) = 125c ? 48.7c = 76.3c shutdown mode applying a high signal to the shutdown pin, sd , or connecting it to the input pin, in , turns the output on. pulling the shutdown pin to 0.3 v or below, or connecting it to ground, turns the output off. in shutdown mode, the quiescent current is reduced to less than 1 a. pcb layout considerations use the following general guidelines when designing printed circuit boards: ? keep the output capacitor as close as possible to the output and ground pins. ? keep the input capacitor as close as possible to the input and ground pins. ? pcb traces with larger cross sectional areas remove more heat from the adp3333. for optimum heat transfer, use thick copper with wide traces. ? connect the nc pins (pin 4, pin 5, pin 6, and pin 8) to ground for better thermal performance. ? the thermal resistance can be decreased by approximately 10% by adding a few square ce ntimeters of copper area to the lands connected to the pins of the ldo. ? use additional copper layers or planes to reduce the thermal resistance. again, connecting the other layers to the gnd and nc pins of the adp3333 is best, but not necessary. when connecting the ground pad to other layers, use multiple vias.
adp3333 rev. b | page 11 of 12 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 23 . 8- lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters ordering guide model temperature range output voltage (v) package description package option branding adp3333arm - 1.5- rl ?40c to +85c 1.5 8- lead msop rm -8 lka adp3333arm - 1.5- rl7 ?40c to +85c 1.5 8- lead msop rm -8 lka adp3333arm - 1.8- rl ?40c to +85c 1.8 8- lead msop rm -8 lkb adp3333arm - 1.8- rl7 ?40c to +85c 1.8 8- lead msop rm -8 lkb adp3333arm - 2.5- rl ?40c to +85c 2.5 8- lead msop rm -8 lkc adp3333arm - 2.5- rl7 ?40c to +85c 2.5 8- lead msop rm -8 lkc adp3333arm - 2.77-rl ?40c to +85c 2.77 8- lead msop rm -8 lkd adp3333arm - 2.77- r7 ?40c to +85c 2.77 8- lead msop rm -8 lkd adp3333arm -3- reel ?40c to +85c 3 8- lead msop rm -8 lke adp3333arm -3- reel7 ?40c to +85c 3 8- lead msop rm -8 lke adp3333arm - 3.15-rl ?40c to +85c 3.15 8- lead msop rm -8 lkf adp3333arm - 3.15- r7 ?40c to +85c 3.15 8- lead msop rm -8 lkf adp3333arm - 3.3- rl ?40c to +85c 3 .3 8- lead msop rm -8 lkg adp3333arm - 3.3 -r l7 ?40c to +85c 3.3 8- lead msop rm -8 lkg adp3333arm -5- reel ?40c to +85c 5 8- lead msop rm -8 lkh adp3333arm -5- reel7 ?40c to +85c 5 8- lead msop rm -8 lkh adp3333armz - 1.5- r7 1 ?40c to +85c 1. 5 8- lead ms op rm -8 l 1x adp3333armz - 1.5 -rl 1 ?40c to +85c 1.5 8- lead msop rm -8 l 1x adp3333armz - 1.8- rl 1 ?40c to +85c 1 .8 8- lead msop rm -8 l 1u adp3333armz - 1.8rl7 1 ?40c to +85c 1 .8 8- lead msop rm -8 l 1u adp3333armz - 2.5- rl 1 ?40c to +85c 2.5 8- lead msop rm -8 l 1v adp3333armz - 2.5- r7 1 ?40c to +85c 2. 5 8- lead msop rm -8 l 1v adp3333armz - 2.77r7 1 ?40c to +85c 2.77 8- lead msop rm -8 l 1y adp3333armz -3- r7 1 ?40c to +85c 3 .0 8- lead msop rm -8 l 1w adp3333 armz - 3.15r7 1 ?40c to +85c 3.15 8- lead msop rm -8 l 1z adp3333armz - 3.3- r7 1 ?40c to +85c 3.3 8- lead msop rm -8 l 20 adp3333armz - 3.3- rl 1 ?40c to +85c 3.3 8- lead msop rm -8 l 20 adp3333armz -5- r7 1 ?40c to +85c 5.0 8- lead msop rm -8 l 21 adp3333armz -5- rl 1 ?40c to +85c 5.0 8- lead ms op rm -8 l 21 1 z = rohs compliant part.
adp3333 rev. b | page 12 of 12 notes ? 2001 C 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 02615 -0- 4/09(b)

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